Device Coupling Effects of Monolithic 3D Inverters

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  • ABSTRACT

    The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness TILD and dielectric constant εr of the inter-layer distance (ILD), the doping concentration Nd (Na), and length Lg of the channel, and the side-wall length LSW where the stacked FETs are coupled are studied. When Nd (Na) < 1016 cm-3 and LSW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when Nd (Na) > 1016 cm-3 or LSW > 20 nm, the shift decreases and increases, respectively. M3INVs with TILD ≥ 50 nm and εr ≤ 3.9 can neglect the interaction between the stacked FETs, but when TILD or εr do not meet the above conditions, the interaction must be taken into consideration.


  • KEYWORD

    3D integrated circuit (3D IC) , Coupling , Monolithic 3D IC , Parasitic extraction , Threshold voltage

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  • [Fig. 1.] Schematics of two types of monolithic 3D inverter cells. (a) 3D schematic of Structure A with a metal layer in the bottom tier, (b) 3D schematic of Structure B without the metal layer, and (c) cross-section of A-A′ in Structure A shown in Fig. 1(a). ML, C, G, D, and S denote the metal layer, contact, gate, drain, and source, respectively. Materials in the structure and doping concentration in the silicon body are denoted by color.
    Schematics of two types of monolithic 3D inverter cells. (a) 3D schematic of Structure A with a metal layer in the bottom tier, (b) 3D schematic of Structure B without the metal layer, and (c) cross-section of A-A′ in Structure A shown in Fig. 1(a). ML, C, G, D, and S denote the metal layer, contact, gate, drain, and source, respectively. Materials in the structure and doping concentration in the silicon body are denoted by color.
  • [Fig. 2.] (a) Inds-Vngs characteristics (linear and logarithmic), (b) transconductance (gm = dInds/dVngs), and (c) capacitance (Cngng, Cnsng, Cdng, Cpgng) of the top transistor in the M3INV cells (Structure A and B) as shown in Fig. 1(a) and (b). Symbols and lines denote Vpgs = 0 and -1 V, respectively. Empty and filled symbols denote Structure A and B, respectively. Here, Lg = 30 nm, TSi = 6 nm, Tox = 1 nm, TILD = 10 nm, Nd (Na) = 1015 cm-3, and Vds = 0.1 V. f = 1 MHz is applied for AC characterization. The subscripts nds, ngs, pgs, ngng, nsng, dng, and pgng denote drain-to-source of the NMOSFET, gate-to-source of the NMOSFET, gate-to-source of the PMOSFET, gate-to-gate of the NMOSFET, source-to-gate of the NMOSFET, drain-to-gate of the NMOSFET, gate of the PMOSFET-to-gate of the NMOSFET, respectively.
    (a) Inds-Vngs characteristics (linear and logarithmic), (b) transconductance (gm = dInds/dVngs), and (c) capacitance (Cngng, Cnsng, Cdng, Cpgng) of the top transistor in the M3INV cells (Structure A and B) as shown in Fig. 1(a) and (b). Symbols and lines denote Vpgs = 0 and -1 V, respectively. Empty and filled symbols denote Structure A and B, respectively. Here, Lg = 30 nm, TSi = 6 nm, Tox = 1 nm, TILD = 10 nm, Nd (Na) = 1015 cm-3, and Vds = 0.1 V. f = 1 MHz is applied for AC characterization. The subscripts nds, ngs, pgs, ngng, nsng, dng, and pgng denote drain-to-source of the NMOSFET, gate-to-source of the NMOSFET, gate-to-source of the PMOSFET, gate-to-gate of the NMOSFET, source-to-gate of the NMOSFET, drain-to-gate of the NMOSFET, gate of the PMOSFET-to-gate of the NMOSFET, respectively.
  • [Fig. 3.] (a) Threshold voltage shift and (b) voltage shift of transconductance (gm) and transcapacitance (Cngng) of the top transistor in the M3INV cell (Structure B) as shown in Fig. 1(b). Here, Nd (Na) = 1015 cm-3 and Vds = 0.1 V. Frequency f = 1 MHz is applied for AC characterization.
    (a) Threshold voltage shift and (b) voltage shift of transconductance (gm) and transcapacitance (Cngng) of the top transistor in the M3INV cell (Structure B) as shown in Fig. 1(b). Here, Nd (Na) = 1015 cm-3 and Vds = 0.1 V. Frequency f = 1 MHz is applied for AC characterization.
  • [Fig. 4.] Threshold voltage shift of the top transistor in the M3INV cell (Structure B) as shown in Fig. 1(b). (a) Material dependence in IML at TILD = 10 and 50 nm, and (b) doping concentration dependence in the silicon channel at TILD = 10 nm. Here Vds = 0.1 V.
    Threshold voltage shift of the top transistor in the M3INV cell (Structure B) as shown in Fig. 1(b). (a) Material dependence in IML at TILD = 10 and 50 nm, and (b) doping concentration dependence in the silicon channel at TILD = 10 nm. Here Vds = 0.1 V.
  • [Fig. 5.] Threshold voltage shift versus side-wall length of the top transistor in the M3INV cell at different TILDs. Here Lg = 30 nm and Vds = 0.1 V.
    Threshold voltage shift versus side-wall length of the top transistor in the M3INV cell at different TILDs. Here Lg = 30 nm and Vds = 0.1 V.