Device Coupling Effects of Monolithic 3D Inverters

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  • ABSTRACT

    The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness TILD and dielectric constant εr of the inter-layer distance (ILD), the doping concentration Nd (Na), and length Lg of the channel, and the side-wall length LSW where the stacked FETs are coupled are studied. When Nd (Na) < 1016 cm-3 and LSW < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when Nd (Na) > 1016 cm-3 or LSW > 20 nm, the shift decreases and increases, respectively. M3INVs with TILD ≥ 50 nm and εr ≤ 3.9 can neglect the interaction between the stacked FETs, but when TILD or εr do not meet the above conditions, the interaction must be taken into consideration.


  • KEYWORD

    3D integrated circuit (3D IC) , Coupling , Monolithic 3D IC , Parasitic extraction , Threshold voltage

  • I. INTRODUCTION

    Three-dimensional (3D) integrated-circuits (ICs) have better performance and energy efficiency, and a smaller footprint in electronic systems than two-dimensional (2D) ICs because of their smaller form factor due to 3D stacking and 3D interconnections [1]. Compared with the currently available through-silicon via (TSV)-based 3D ICs [2], the monolithic 3D IC (M3IC) [3-12], in which each circuit layer is thin and is fabricated directly over the previous circuit layers on the same substrate, is a promising technology that enables ultrafine-grained vertical integration of devices and interconnections with the conventional monolithic inter-tier vias (MIVs) to connect the various layers.

    There have been extensive studies of process, device, and circuit technologies for the M3IC [3-12]. SRAM and inverters utilizing dynamic threshold voltage (VTH) modification thanks to the electrical coupling between stacked top and bottom metal-oxide-semiconductor field-effect transistors (MOSFETs) have been demonstrated when the inter-layer dielectric (ILD) is very thin (tens of nanometers) [12]. However, to our knowledge, no studies have been published that evaluate a regime in which the electrical coupling between the stacked FETs is either considered or not. Therefore, to design and analyze M3ICs precisely with an ultra-thin ILD, regimes in which the electrical coupling between the stacked FETs is included must be systematically investigated.

    In this paper, the electrical coupling between the stacked top/bottom FETs in two types of monolithic 3D inverter (M3INV), of which one includes a metal layer (ML) in the bottom tier and the other does not include a ML, will be systematically investigated using a 3D device simulator. Device characteristics of the two types of M3INV will be surveyed in terms of electrical coupling between the stacked top/bottom FETs (Section II). Next, the regime of the sizes and materials of the ILD, as well as the doping concentration and length of channel where the stacked FETs are coupled will be studied (Section III). Finally, Section IV will conclude this paper.

    II. DEVICE CHARACTERISTICS OF THE M3INV

    Fig. 1 shows the schematics of two examples of typ